For certain high-speed applications, low voltage core devices (which are generally faster than high voltage input/output (IO) devices) are often used, for example, in a differential reference clock buffer. This clock buffer typically needs to interface with input signals (e.g., low voltage positive emitter coupled logic (LVPECL), low voltage differential signal (LVDS), common mode logic (CML), etc.) having a variety of signal levels and common modes.
In order to accommodate signals having such a wide variety of signal levels and common modes, inputs to the buffer are typically AC coupled, such as, for example, by placing coupling capacitors in series with the respective inputs. During boundary scan, or an alternative test mode, however, when a signal applied to a given input is toggled at a much lower rate, the coupling capacitor corresponding to the given input needs to be bypassed. Typically, in a bypass mode of operation, a high voltage n-channel metal-oxide-semiconductor (NMOS) switch is used to selectively shunt the coupling capacitor in response to a bypass signal. A voltage translator circuit is generally not used to translate the bypass signal because the voltage translator circuit is known to be susceptible to electrostatic discharge (ESD) events (e.g., charged device model (CDM)), and use of a noisy high voltage IO supply can be avoided.
One problem exhibited by conventional bypass circuitry is that the high voltage NMOS switch commonly used to shunt the coupling capacitor often fails to fully short out the capacitor. A high voltage p-channel metal-oxide-semiconductor (PMOS) switch can be connected in parallel with the NMOS switch to help shunt the coupling capacitor during bypass mode. However, a high voltage control signal would be required in order to turn off this PMOS device under normal operation of the buffer, thereby necessitating a voltage level translator circuit and a high voltage power supply, which is undesirable.
Accordingly, there exists a need for improved techniques for bypassing AC coupled inputs of a circuit which does not suffer from one or more of the above-noted problems exhibited by conventional bypass circuitry.